1. Field of the Invention
This invention relates in general to analog-to-digital converter systems, and more particularly to a high speed analog-to-digital converter suitable for processing video signals.
2. Description of Related Art
A variety of electronic devices, such as computers, monitors, flat panel displays, wireless communication devices, to name just a few, utilize high speed electronic signals, e.g., clock signals, video signals, spread spectrum and digital wireless communication signals, etc. A predominant trend in electronic devices is the use of digital signals. As is well known to those of ordinary skill in the art, there are many advantages to representing electronic signals in digital signal form in many such electronic devices.
An analog-to-digital converter (ADC) is typically utilized to sample an analog electronic signal at a point in time and to convert the sampled electronic signal to a digital representation thereof. The ADC, in one common configuration, typically includes a resistive ladder network electrically coupled to a plurality of comparators that are respectively referenced to a plurality of reference voltages provided by said resistive network. The ADC compares the voltage amplitude of an input signal to the plurality of reference voltages and provides an output signal that is a digital representation of the input signal at a point in time.
Regrettably, conventional ADC implementations have been typically designed for electronic signaling that is much slower than needed for handling the higher speed of video signaling. For high speed signaling applications, such as video signaling, ADCs have unique requirements that in the past have not been met by conventional ADC technology.
First, referring to FIG. 1, ADCs typically sample an input signal 102 utilizing an input network of resistors in a resistor ladder 104 coupled to comparators 110 comparing each progressive step in the ladder 108 to a different reference voltage value. Each comparator 110, therefore, provides a progressive detection step in determining a digital representation of an input signal 102. Since there is a continuous need for higher precision in the final digital representation that is output from the ADC that is sampling an analog signal, every additional bit line typically multiplies the number of comparators by at least a factor of 2. This in turn increases the expense and complexity of the ADC circuits. Secondly, besides the added expense of the more complex integrated circuits, the increased number of circuit elements additionally increases the opportunities for circuit failures and hence detrimentally impacts overall quality of the ADC as perceived by customers. Thirdly, the higher number of comparators necessary for higher resolution increases the power consumption of the ADC circuits thereby decreasing the potential speed of driving these circuits at a given power budget. For very high speed circuits it is imperative to drive the ADC at a maximum speed to track the very high speed signals such as in video signaling. Therefore, for a given power budget and for maximum speed for an ADC it is critical to keep the comparator count low.
Additionally, there is a significant need to provide enhanced resolution at the output of modern ADCs. The higher resolution requirement has called for higher numbers of comparators and related circuit elements. This tends to increase the cost of the ADC. At the same time, the cost of such ADCs must be kept as low as possible for commercial viability. Competitive pressures in many markets, especially for high volume products, require that component costs, such as for a high speed ADC, be kept very low. Therefore, there are seriously opposing technical design constraints for providing a high resolution ADC while keeping the cost low.
To increase the resolution of a digital output signal, prior art designs have added interpolation stages on the output side of an ADC. For example, as shown in FIG. 1, the output of the comparators 110 normally would couple directly to output capture latches 130. However, interpolated output latches 140 and a second ladder 120, arranged as shown, can be added to the output side of an ADC to increase (in the example shown in FIG. 1, multiply by 4) the total number of outputs 124. As can be seen, although the number of output lines can be significantly increased, the resolution steps for sampling the input signal 102 are still limited to the number of comparators and associated capture latches 130. Specifically, an interpolating ADC has a number of input stages and then has a structure, typically a resistor string and/or capacitors, that interpolates between output voltages of adjacent input stages to provide additional output stages that allow making more decisions about signal granularity than there are input stages. For example, an ADC may have 16 input stages and be designed for four time interpolation or 64 output stages. For each input stage there are four output stages and an interpolating structure spans all the array of input stages to interpolate the output voltage across all the 64 output stages. This allows finer granularity at the output signal.
An alternative design in the prior art, as illustrated in FIG. 2, utilized a xe2x80x9ccoarse measurementxe2x80x9d ADC 202, a xe2x80x9cfine measurementxe2x80x9d ADC 218, a digital to analog converter (DAC) 212, a subtraction stage 214, and an amplifier stage 216, to provide a sub-ranging approach to convert an analog input signal 204 to a digital output signal 210, 222. Note that the xe2x80x9ccoarse measurementxe2x80x9d output 210 provides the most significant bits (upper range of digital signal output) and the xe2x80x9cfine measurementxe2x80x9d output 222 provides the least significant bits (lower range of digital signal output) of the digital output signal 210, 222. Also, note that the xe2x80x9ccoarse measurementxe2x80x9d ADC 202 operates relative to a first reference voltage 206, 208, while the xe2x80x9cfine measurementxe2x80x9d ADC 218 operates relative to a second reference voltage 220. Although each ADC may utilize a lower number of comparator steps, the overall ADC circuit 200 does require the added components of the DAC 212, the subtraction stage 214, and the amplifier stage 216. This sub-ranging approach, unfortunately, adds overall circuit complexity and the additional DAC stage adds timing delay to the overall analog to digital conversion process which may tend to reduce the sampling speed of the overall ADC circuit 200. This added timing delay reduces the maximum speed that a high speed ADC can sample analog signals, which conflicts with the requirement for a high speed ADC to sample very high speed signals such as video signals.
Thus, there is a need to overcome the disadvantages of the prior art, such as discussed above, and in particular to improve the resolution and speed of conversion of the analog electronic signal to a digital representation thereof while operating within a power consumption constraint and while keeping product cost low.